The present invention relates to integrated circuits and in particular, to an electronic description of an integrated circuit that is encrypted to prevent the details of the circuit from being revealed while still allowing simulation of the integrated circuit, and in particular, allowing gate delays to be simulated.
Complex integrated circuits, such as “system on chip” (SOC) designs, can be constructed from circuit “building blocks” developed by different companies. The building blocks are assembled by combining electronic files describing each building block to produce the necessary integrated circuit masks needed to produce the ultimate integrated circuit.
These building blocks are often referred to as intellectual property (IP) cores, reflecting the fact that it is the underlying design (the intellectual property) that is sold by the designer as opposed to an actual integrated circuit. The ability to license IP cores provides substantial efficiency in the design of complex circuit elements by allowing the costs of developing an IP core to be shared among multiple manufacturers.
The abstract IP core is captured in an electronically readable circuit-level schematic describing each component, for example, logic gates and their interconnection, together with a functional description of the inputs and outputs to the IP core (the functional specification). While the sale of an IP core may include this entire functional specification (a so-called “soft” core), it is also possible to sell an electronic description of an IP core that provides only layout information and the functional description of the inputs and outputs without the circuit level schematic. This so-called “hard” core allows fabrication of the IP core but does not reveal information about the internal circuit configuration or components, preventing ready copying or modification of the IP core.
Normally a hard-core license for an IP core will be cheaper than a soft-core license because the hard-core license, by hiding the circuit design, reduces the risk that the purchaser will be able to compete with or develop commercial alternatives to the IP core or that the intellectual property of the IP core will be revealed. Nevertheless, the less-expensive hard-core license has significant drawbacks. Because the details of the underlying circuit are hidden, it is not possible to simulate the IP core alone or in combination with the other building block circuits. The ability to simulate operation of the IP core allows better integration with other circuit elements, for example, by revealing operating limitations such as signal propagation delays that need to be accommodated. Simulation is also important to identify how component faults will affect the IP core. Such fault simulation allows the end user to construct more efficient “built-in self test” (BIST) logic that can be used to test the operation of the IP core during manufacture. Generally, BIST logic identifies bit patterns or vectors that are used to detect faults in a logic circuit.
The practical ability to select only between a hard-core or soft-core licensing model substantially limits the market for IP cores in many important applications where IP core simulation is required but where purchasing a soft-core license is too costly.
US patent application 2015/0188661, assigned to the assignee of the present application and hereby incorporated by reference (henceforth the Logical Encryption Invention), describes a system for producing an encrypted description of the logic elements (gates) of an integrated circuit that allows operation of the integrated circuit to be simulated without the gates being identifiable as to function. The encrypted description of logic elements can be used by simulators without decryption. This invention makes it possible to license IP cores in a way that provides the intellectual property protection associated with hard-core licensing while allowing the logical simulation capabilities associated with soft-core licensing. This simulation permits fault analysis and the development of bit vectors for BIST logic.
In simulating an integrated circuit, it can also be important to be able to accurately model signal propagation delays through the integrated circuit. The Logical Encryption Invention identifies the gates and their interconnection (although not their function) and thus allows rough estimates for gate delays to be calculated, for example, by assuming all gates have an average standard gate delay. Such an approach is inadequate for sophisticated circuit simulation where accurate propagation delays need to be calculated. Generally, gate delays vary meaningfully between different types of gates both according to their logical function and their circuit level architecture (e.g., size of transistors, etc.).
Revealing detailed gate delay information for each gate can undercut the intellectual property protection of the integrated circuit. For example, it may be possible to deduce the function of gate from its gate delay.
Equally important, independent of an interest in preserving the secrecy of the gate functions, the manufacturer may wish to preserve secrecy with respect to gate delay values themselves. Gate delays of each gate instance are often tailored by the manufacturer for improved integrated circuit performance, and this information also represents important intellectual property.